1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (LEI: Large Scale Integration, hereinafter referred to as “LEI”) manufacturing method, and more particularly to a technology effective in the suppression of parasitic elements occurring between elements and wiring in analog layout design, suppression of variation occurring between elements, and element placement area optimization.
2. Description of the Related Art
Recently, together with advances in LEI manufacturing technology, progress has been made in achieving larger scale, higher speed, and greater precision. Together with this, with regard to wiring (routing), the influence of wiring length, wiring width, inter-wiring distance, inter-layer contacts, substrate-relative and such-like parasitic elements, process variation (film thickness, lithographic etching, etc.), and so forth, has become conspicuous. With regard to elements, also, the effects of process variation (film thickness, ion injection density, lithographic etching, length, width, area, etc.) And so forth have become marked. These have become major problems as they are linked to degradation of LEI performance and quality. With conventional technology, automatic prediction and extraction has been performed of design constraints such as element pairing and grouping from connectional relationships of applicable circuits when performing automatic placement, and automatic placement and routing has been carried out based on these extracted constraints. (See, for example, Unexamined Japanese Patent Publication No. 2003-85224 (page 24, FIG. 1)).
However, constraints provided in this way are set based on experience, and it has not been possible to satisfy characteristics at one time even assuming that all the constraints are observed. There is another method whereby parasitic elements are provided as placement and routing constraints (see, for example, Unexamined Japanese Patent Publication No. 2002-93912 (page 5, FIG. 1)), but automatic placement reflecting the actually extracted constraints is not realized in either example.
However, with conventional technology, although it is possible for automatic extraction of placement and routing constraints necessary for automatic placement and routing to be implemented by a number of means, with regard to placement and routing constraints actually obtained by a conventional method, a means of reflecting constraints provided within a real-valued range, particularly for parasitic elements and inter-element variation, has not been realized.